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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
2-Mbit (128K x 16) Static RAM
Features
* Very high speed -- 55 ns * Temperature Ranges -- Industrial: - 40C to + 85C -- Automotive: - 40C to + 125C * Pin-compatible with the CY62137V * Ultra-low active power -- Typical active current: 1.5 mA @ f = 1 MHz -- Typical active current: 7 mA @ f = fMax (55 ns speed) * Low and ultra-low standby power * Easy memory expansion with CE and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Available in Pb-free and non Pb-free 48-ball FBGA package ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The devices also has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.
Functional Description[1]
The CY62137CV30/33 and CY62137CV are high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE CE OE BLE CE BHE BLE Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
A11
Power -Down Circuit
Cypress Semiconductor Corporation Document #: 38-05201 Rev. *G
*
198 Champion Court
A12 A13 A14 A15 A16
*
San Jose, CA 95134-1709 * 408-943-2600 Revised July 21, 2006
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Product Portfolio
Power Dissipation Operating, ICC (mA) VCC Range (V) Product CY62137CV30LL Range Industrial Min. 2.7 Typ.[2] 3.0 Max. 3.3 f = 1 MHz Speed (ns) 55 70 CY62137CV30LL CY62137CV33LL CY62137CVSL Automotive Industrial Industrial 2.7 3.0 2.7 3.0 3.3 3.3 3.3 3.6 3.6 70 55 70 Typ.[2] 1.5 1.5 1.5 1.5 1.5 Max. 3 3 3 3 3 f = fMax Typ.[2] 7 5.5 5.5 7 5.5 Max. 15 12 15 15 12 2 5 1 15 15 5 Standby, ISB2 (A) Typ.[2] 2 Max. 10
Pin Configuration[3, 4]
48-ball VFBGA Top View
1 BLE I/O8 I/O9 VSS VCC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O6 I/O7 NC A B C D E F G H
I/O12 DNU A14 A12 A9
I/O14 I/O13 I/O15 NC NC A8
Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. 3. NC pins are not connected to the die. 4. E3 (DNU) pin have to be left floating or tied to VSS to ensure proper operation.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to +150C Ambient Temperature with Power Applied..............................................-55C to +125C Supply Voltage to Ground Potential -0.5V to VCC(max) + 0.5V DC Voltage Applied to Outputs in High-Z State[5] .................................... -0.5V to VCC + 0.3V DC Input Voltage[5] ................................. -0.5V to VCC + 0.3V Output Current into Outputs (LOW) .............................20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Device CY62137CV30 CY62137CV33 CY62137CV Range Industrial Ambient Temperature TA VCC 3.0V to 3.6V 2.7V to 3.6V
-40C to +85C 2.7V to 3.3V
CY62137CV30 Automotive -40C to +125C 2.7V to 3.3V
Electrical Characteristics Over the Operating Range
CY62137CV30-55 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC Ind'l Auto GND < VO < VCC, Output Disabled f = fMax = 1/tRC Ind'l Auto VCC = 3.3V Ind'l IOUT = 0mA CMOS Levels Auto Ind'l Auto ISB1 Automatic CE Ind'l CE > VCC - 0.2V Power-down V > VCC - 0.2V or VIN < 0.2V, Current -- CMOS Inputs IN f = fMax (Address and Data only), f=0 (OE, WE, BHE and BLE) Auto Automatic CE CE > VCC - 0.2V Power-down VIN > VCC - 0.2V or VIN < 0.2V Current -- CMOS Inputs f = 0, VCC = 3.3V Ind'l Auto 2 10 7 15 -1 +1 Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V 2.2 -0.3 -1 CY62137CV30-70 Min. Typ.[2] Max. Min. Typ.[2] Max. Unit 2.4 0.4 VCC +0.3 0.8 +1 2.2 -0.3 -1 -2 -1 -2 5.5 5.5 1.5 3 1.5 1.5 2 2.4 0.4 VCC +0.3 0.8 +1 +2 +1 +2 12 15 3 3 10 A mA A V V V V A
IOZ
ICC
f = 1 MHz
2 2 10 2 2
15 10 15 A
ISB2
Note: 5. VIL(min.) = -2.0V for pulse durations less than 20 ns.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Electrical Characteristics Over the Operating Range (continued)
CY62137CV33-55 Parameter VOH Description Output HIGH Voltage Test Conditions IOH = -1.0 mA VCC = 3.0V VCC = 2.7V VOL Output LOW Voltage IOL = 2.1 mA VCC = 3.0V VCC = 2.7V VIH VIL IIX IOZ ICC Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC 2.2 -0.3 -1 -1 7 1.5 5 VCC + 0.3 0.8 +1 +1 15 3 15 2.2 -0.3 -1 -1 5.5 1.5 5 0.4 Min. 2.4 Typ.[2] Max. CY62137CV-70 Min. Typ.[2] 2.4 2.4 0.4 0.4 VCC + 0.3 0.8 +1 +1 12 3 15 A Max. Unit V V V V V V A A mA
Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current f = fMax = 1/tRC f = 1 MHz VCC = 3.6V IOUT = 0 mA CMOS Levels
ISB1
Automatic CE CE > VCC - 0.2V Power-down V > VCC - 0.2V or VIN < 0.2V, Current --CMOS Inputs IN f = fMax (Address and Data Only), f=0 (OE, WE, BHE, and BLE) Automatic CE LL CE > VCC - 0.2V Power-down VIN > VCC - 0.2V or Current --CMOS Inputs VIN < 0.2V, f = 0, VCC = 3.6V SL
ISB2
5 5
15 15
5 1
15 5
A
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF
Thermal Resistance[6]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, 2-layer printed circuit board FBGA 55 16 Unit C/W C/W
Note: 6. Tested initially and after any design or process changes that may affect these parameters.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2
VCC 10% GND Rise TIme: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT VTH
Parameters R1 R2 RTH VTH
3.0V 1105 1550 645 1.75
3.3V 1216 1374 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.5V LL CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V SL Ind'l Auto Ind'l 0 tRC Conditions Min. 1.5 1 Typ.[4] Max. Vcc(max) 6 8 4 ns ns A Unit V
tCDR[6] tR[7]
Chip Deselect to Data Retention Time Operation Recovery Time
Data Retention Waveform[8]
DATA RETENTION MODE VCC CE or
VCC(min.)
tCDR
VDR > 1.5 V
VCC(min.)
tR
BHE.BLE
Notes: 7. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 8. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Switching Characteristics Over the Operating Range[9]
55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE[11] tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle[13] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BHE/BLE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[10, 12] 10 55 45 45 0 0 40 50 25 0 20 10 70 60 60 0 0 45 60 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[10] OE HIGH to High-Z[10, 12] 10 20 0 55 55 5 20 5 25 0 70 70 5 20 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. 70 ns Max. Unit
CE LOW to Low-Z[10] CE HIGH to High-Z[10, 12]
CE LOW to Power-up CE HIGH to Power-down BHE/BLE LOW to Data Valid BHE/BLE LOW to Low-Z[10]
BHE/BLE HIGH to High-Z[10, 12]
WE HIGH to Low-Z[10]
Notes: 9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. If both byte enables are toggled together this value is 10 ns. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC ADDRESS tAA DATA VALID
tOHA DATA OUT PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC CE tACE OE
tDOE
tPD tHZCE
tHZOE
BHE/BLE
ttLZOE LZOE
tHZBE
tDBE
tLZBE HIGH IMPEDANCE DATA OUT tLZCE tPU VCC SUPPLY CURRENT 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 14. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[13, 17, 18]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)[13, 17, 18]
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Notes: 17. Data I/O is high-impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[18]
.
tWC ADDRESS
CE tAW BHE/BLE tSA WE tSD DATA I/O NOTE 19 tHZWE DATA VALID IN tLZWE tHD tBW tPWE tHA
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18]
tWC ADDRESS
CE tAW tBW tSA WE tSD DATA I/O tHD tPWE tHA
BHE/BLE
NOTE 19
tHZWE
DATA VALID IN tLZWE
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Truth Table
CE H X L L L L L L L L L WE X X H H H L L L H H H OE X X L L L X X X H H H BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High-Z High-Z Data Out (I/O0-I/O15) High Z (I/O8-I/O15); Data Out (I/O0-I/O7) Data Out (I/O8-I/O15); High Z (I/O0-I/O7) Data In (I/O0-I/O15) High Z (I/O8-I/O15); Data In (I/O0-I/O7) Data in (I/O8-I/O15); High Z (I/O0-I/O7) High-Z High-Z High-Z Mode Deselect/Power-down Deselect/Power-down Read Read Read Write Write Write Output Disabled Output Disabled Output Disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62137CV30LL-55BVI CY62137CV30LL-55BVXI CY62137CV33LL-55BVI 70 CY62137CV30LL-70BAI CY62137CV30LL-70BVI CY62137CVSL-70BAI CY62137CVSL-70BAXI CY62137CV30LL-70BAE CY62137CV30LL-70BVE CY62137CV30LL-70BVXE 51-85096 51-85150 51-85096 51-85150 51-85096 Package Diagram 51-85150 Package Type 48-ball FBGA (6 x 8 x 1 mm) 48-ball FBGA (6 x 8 x 1 mm) (Pb-free) 48-ball FBGA (6 x 8 x 1 mm) 48-ball FBGA (7 x 7 x 1.2 mm) 48-ball FBGA (6 x 8 x 1 mm) 48-ball FBGA (7 x 7 x 1.2 mm) 48-ball FBGA (7 x 7 x 1.2 mm) (Pb-free) 48-ball FBGA (7 x 7 x 1.2 mm) 48-ball FBGA (6 x 8 x 1 mm) 48-ball FBGA (6 x 8 x 1 mm) (Pb-free) Automotive Industrial Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Package Diagrams
48-ball FBGA (7 x 7 x 1.2 mm) (51-85096)
TOP VIEW
BOTTOM VIEW PIN 1 CORNER O0.05 M C O0.25 M C A B O0.300.05(48X)
PIN 1 CORNER (LASER MARK) 12 A B C 7.000.10 5.25 D E F G H 7.000.10 0.75 3 4 5 6
6
5
4
3
2
1 A B C D E
2.625
F G H
A
A
1.875 0.75
B
7.000.10 3.75 B 7.000.10
0.530.05
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85096-*F
SEATING PLANE 0.36 C
1.20 MAX.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 8.000.10 8.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85150-*D
SEATING PLANE 0.26 MAX. C 1.00 MAX
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62137CV30/33 MoBL(R) CY62137CV MoBL(R)
Document History Page
Document Title: CY62137CV30/33 MoBL(R) and CY62137CV MoBL(R) 2-Mbit (128K x 16) Static RAM Document Number: 38-05201 REV. ** *A *B *C ECN NO. 112393 114015 117064 118122 Issue Date 02/19/02 04/25/02 07/12/02 09/10/02 Orig. of Change GAV JUI MGN MGN Description of Change New Data Sheet (advance information) Added BV package diagram Changed from Advance Information to Preliminary Changed from Preliminary to Final Added new part number: CY62137CV with wider voltage (2.7V - 3.6V) Added new SL power bin for new part number For TAA = 55 ns, improved tPWE min. from 45 ns to 40 ns For TAA = 70 ns, improved tPWE min. from 50 ns to 45 ns For TAA = 70 ns, improved tLZWE min. from 5 ns to 10 ns Improved Typ. ICC spec to 7 mA (for 55 ns) and 5.5 mA (for 70 ns) Improved Max ICC spec to 15 mA (for 55 ns) and 12 mA (for 70 ns) For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns Changed upper spec. for Supply Voltage to Ground Potential to VCC(max) + 0.5V Changed upper spec. for DC Voltage Applied to Outputs in High-Z State and DC Input Voltage to VCC + 0.3V Added Automotive Information in Operating Range, DC and Ordering Information Table Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Updated the ordering information table and replaced the Package name column with Package diagram Removed part number CY62137CV25 from the product offering Updated the ordering information table
*D
118761
09/23/02
MGN
*E *F
343877 419237
See ECN See ECN
PCI ZSD
*G
486789
See ECN
VKN
Document #: 38-05201 Rev. *G
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